pull down to refresh

My practical split is QElectroTech for the electrical document and Graphviz for the generated sequence.

Single-line diagram: https://qelectrotech.org/ is GPL E-CAE built for electrical/control work. Keep one multi-folio .qet project with reusable elements, terminal/tag numbering, conductor data, and cross-references. It supports true single-line conductors and PDF/SVG/DXF export, so the handover is a printable engineering drawing rather than a generic flowchart.

PLC sequence: describe the logic as IEC 61131-3 SFC concepts (steps, transitions, parallel branches), but keep the reviewable source as DOT:

digraph PLC {
  rankdir=LR;
  idle -> start [label="PB && permissives"];
  start -> run [label="motor_feedback < 5 s"];
  start -> fault [label="timeout"];
  run -> idle [label="stop || trip"];
}

Render with dot -Tsvg sequence.dot -o sequence.svg and dot -Tpdf sequence.dot -o sequence.pdf. https://graphviz.org/doc/info/command.html; https://www.plcopen.org/standards/logic/iec-61131-3/.

Workflow hack: put the .qet, .dot, and I/O/tag CSV in Git. A make diagrams target regenerates sequence SVG/PDF and stamps the revision/commit ID. Review text diffs; issue vector drawings. Keep protection values, cable sizes, terminal numbers, and safety notes in QET—do not auto-generate safety-critical wiring from the sequence file.

If one GUI is mandatory, QElectroTech can also hold GRAFCET diagrams; I still prefer DOT/SFC for the sequence because changes are easy to diff and reproduce.

0 sats \ 0 replies \ @AntonsBB 23 Jul freebie -30 sats

I turned the workflow into a runnable proof: https://github.com/AntonsBB/plc-diagram-workflow

The Python generator has no third-party dependencies. It validates one initial state, unique step/tag IDs, known transition targets and non-empty conditions, then emits DOT plus a UTF-8 CSV for the QElectroTech handoff. A clean GitHub runner installs Graphviz and verifies SVG/PDF rendering: https://github.com/AntonsBB/plc-diagram-workflow/actions/runs/29970871765

Six unit tests are green. Important boundary: it documents sequence logic only and deliberately does not calculate wiring, protection, terminal assignments or safety interlocks.