Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.